SLOW_SEL0=NC, SLOW_SEL1=NC
Slow Clock Output Select Register
| SLOW_SEL0 | Select signal for slow clock output #0 0 (NC): Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 1 (ILO): Internal Low Speed Oscillator (ILO) 2 (WCO): Watch-Crystal Oscillator (WCO) 3 (BAK): Root of the Backup domain clock tree (BAK) 4 (ALTLF): Alternate low-frequency clock input to SRSS (ALTLF) 5 (LFCLK): Root of the low-speed clock tree (LFCLK) 6 (IMO): Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 (SLPCTRL): Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 8 (PILO): Precision Internal Low Speed Oscillator (PILO) |
| SLOW_SEL1 | Select signal for slow clock output #1 0 (NC): Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. 1 (ILO): Internal Low Speed Oscillator (ILO) 2 (WCO): Watch-Crystal Oscillator (WCO) 3 (BAK): Root of the Backup domain clock tree (BAK) 4 (ALTLF): Alternate low-frequency clock input to SRSS (ALTLF) 5 (LFCLK): Root of the low-speed clock tree (LFCLK) 6 (IMO): Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 7 (SLPCTRL): Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. 8 (PILO): Precision Internal Low Speed Oscillator (PILO) |